A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this paper. The power consumption and general characteristics of the SERF adder...
In this paper a new low power and high performance adder cell using a new design style called "Bridge" is proposed. The bridge design style enjoys a high degree of regula...
This paper describes a new mixed-swing topology for dual-rail domino logic that results in a simultaneous energy and delay reduction. HSPICE simulation results for a 1-bit full ad...
Bharath Ramasubramanian, Herman Schmit, L. Richard...
In this paper, we survey various designs of low-power full-adder cells from conventional CMOS to really inventive XOR-based designs. We further describe simulation experiments tha...