32 search results - page 3 / 7 » A New Full Adder Cell for Low-Power Applications |
ASAP
2002
IEEE
14 years 12 days ago
2002
IEEE
This paper introduces PAPA: Packed Arithmetic on a Prefix Adder, a new approach to parallel prefix adder design that supports a wide variety of packed arithmetic computations, inc...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
CORR
2010
Springer
13 years 4 months ago
2010
Springer
Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power...
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
DFT
1999
IEEE
13 years 11 months ago
1999
IEEE
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...