32 search results - page 4 / 7 » A New Full Adder Cell for Low-Power Applications |
VLSID
2006
IEEE
14 years 1 months ago
2006
IEEE
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel ...
TC
1998
13 years 7 months ago
1998
—This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs)...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit ...
SOCC
2008
IEEE
14 years 1 months ago
2008
IEEE
In this paper a new ultra low power SRAM cell is proposed. In the proposed SRAM topology, additional circuitry has been added to a standard 6T-SRAM cell to improve the static nois...
ICCAD
2002
IEEE
14 years 12 days ago
2002
IEEE
The paper describes the folding method of logic functions to reduce the size of memories for keeping the functions. The folding is based on the relation of fractions of logic func...