32 search results - page 5 / 7 » A New Full Adder Cell for Low-Power Applications |
EUROGP
2000
Springer
13 years 11 months ago
2000
Springer
1 The function level evolvable hardware approach to synthesize the combinational multiple-valued and binary logic functions is proposed in rst time. The new representation of logic...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
- Designing a power-gating structure with high performance in the active mode and low leakage and short wakeup time during standby mode is an important and challenging task. This p...
DFT
2002
IEEE
14 years 12 days ago
2002
IEEE
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
ISLPED
1999
ACM
13 years 11 months ago
1999
ACM
While guarded evaluation has proven an effective energy saving technique in arithmetic circuits, good methodologies do not exist for determining when and how to guard for maximal ...
DFT
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...