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ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
15 years 10 months ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
ISCA
2006
IEEE
133views Hardware» more  ISCA 2006»
15 years 10 months ago
TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-time
RAID architectures have been used for more than two decades to recover data upon disk failures. Disk failure is just one of the many causes of damaged data. Data can be damaged by...
Qing Yang, Weijun Xiao, Jin Ren
ISCAS
2006
IEEE
160views Hardware» more  ISCAS 2006»
15 years 10 months ago
Address-event image sensor network
We describe a sensor network based on smart requirements of the network. This will provide a new approach imager sensors able to extract events of interest from a scene. for compos...
Eugenio Culurciello, Andreas Savvides
ISM
2006
IEEE
81views Multimedia» more  ISM 2006»
15 years 10 months ago
Water Jets as Pixels: Water Fountains as Both Sensors and Displays
We propose a hydraulic user interface consisting of an array of spray jets and the appropriate fluid sensing and fluid flow control systems for each jet, so that the device fun...
Steve Mann, Michael Georgas, Ryan E. Janzen
ISPASS
2006
IEEE
15 years 10 months ago
Improved stride prefetching using extrinsic stream characteristics
Stride-based prefetching mechanisms exploit regular streams of memory accesses to hide memory latency. While these mechanisms are effective, they can be improved by studying the p...
Hassan Al-Sukhni, James Holt, Daniel A. Connors
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