945 search results - page 35 / 189 » A New Method for Design of Robust Digital Circuits |
DFT
2008
IEEE
14 years 3 months ago
2008
IEEE
Nanoelectronic components are expected to suffer from very high error rates, implying the need for hardening techniques. We propose a fine-grained approach to harden a promising...
ICCAD
2002
IEEE
14 years 5 months ago
2002
IEEE
For many years, CMOS process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reach...
GLVLSI
2005
IEEE
14 years 2 months ago
2005
IEEE
Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose a new domino circuit for high fan-in ...
DAC
1997
ACM
14 years 1 months ago
1997
ACM
Abstract - This paper describes the development of a concurrent methodology for standard cell library generation. Use of a novel physical design automation method enables a high de...
DAC
2005
ACM
14 years 10 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...