Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven h...
This paper introduces a new design method for multi-agent systems (MAS) that incorporate logic programming. The DigitalFriend is an example of a MAS with a built-in logic language...
Steve Goschnick, Sandrine Balbo, Leon Sterling, Ch...
Designing asynchronous circuits by reusing existing synchronous tools has become a promising solution to the problem of poor CAD support in asynchronous world. A straightforward w...
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
Michael Krasnicki, Rodney Phelps, James R. Hellums...
ct Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particul...
David Blaauw, Vladimir Zolotov, Savithri Sundaresw...