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» A New Method for Design of Robust Digital Circuits
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ACSAC
2005
IEEE
14 years 2 months ago
Fault Attacks on Dual-Rail Encoded Systems
Fault induction attacks are a serious concern for designers of secure embedded systems. An ideal solution would be a generic circuit transformation that would produce circuits tha...
Jason Waddle, David Wagner
GECCO
2006
Springer
207views Optimization» more  GECCO 2006»
14 years 20 days ago
Both robust computation and mutation operation in dynamic evolutionary algorithm are based on orthogonal design
A robust dynamic evolutionary algorithm (labeled RODEA), where both the robust calculation and mutation operator are based on an orthogonal design, is proposed in this paper. Prev...
Sanyou Y. Zeng, Rui Wang, Hui Shi, Guang Chen, Hug...
VLSID
2002
IEEE
79views VLSI» more  VLSID 2002»
14 years 9 months ago
A Power Minimization Technique for Arithmetic Circuits by Cell Selection
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit ...
Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, ...
DAC
1999
ACM
14 years 1 months ago
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing
We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence i...
Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, J...
DAC
1999
ACM
14 years 1 months ago
On ILP Formulations for Built-In Self-Testable Data Path Synthesis
In this paper, we present a new method to the built-in selftestable data path synthesis based on integer linear programming (ILP). Our method performs system register assignment, ...
Han Bin Kim, Dong Sam Ha, Takeshi Takahashi