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» A New Method for Design of Robust Digital Circuits
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CICC
2011
106views more  CICC 2011»
12 years 9 months ago
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of...
Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D....
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 3 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
ICC
2007
IEEE
115views Communications» more  ICC 2007»
14 years 28 days ago
Super-Wideband SSN Suppression in High-Speed Digital Communication Systems by Using Multi-Via Electromagnetic Bandgap Structures
With the advance of semiconductor manufacturing, There are many approaches to deal with these problems. EDA, and VLSI design technologies, circuits with even higher Adding discrete...
MuShui Zhang, YuShan Li, LiPing Li, Chen Jia
ICONIP
2010
13 years 7 months ago
A New Framework for Small Sample Size Face Recognition Based on Weighted Multiple Decision Templates
In this paper a holistic method and a local method based on decision template ensemble are investigated. In addition by combining both methods, a new hybrid method for boosting the...
Mohammad Sajjad Ghaemi, Saeed Masoudnia, Reza Ebra...
DATE
2005
IEEE
116views Hardware» more  DATE 2005»
14 years 2 months ago
Uniformly-Switching Logic for Cryptographic Hardware
Recent work on Differential Power Analysis shows that even mathematically-secure cryptographic protocols may be vulnerable at the physical implementation level. By measuring energ...
Igor L. Markov, Dmitri Maslov