73 search results - page 9 / 15 » A New Pipelined Array Architecture for Signed Multiplication |
ICDE
2003
IEEE
14 years 9 months ago
2003
IEEE
The long-running nature of continuous queries poses new scalability challenges for dataflow processing. CQ systems execute pipelined dataflows that may be shared across multiple q...
MICRO
2002
IEEE
14 years 20 days ago
2002
IEEE
Recently, graphics hardware architectures have begun to emphasize versatility, offering rich new ways to programmatically reconfigure the graphics pipeline. In this paper, we exp...
ISPD
2003
ACM
14 years 1 months ago
2003
ACM
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
Wide SIMD-based GPUs have evolved into a promising platform for running general purpose workloads. Current programmable GPUs allow even code with irregular control to execute well...
VLSID
2001
IEEE
14 years 8 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...