Sciweavers

104 search results - page 10 / 21
» A New Reactive Processor with Architectural Support for Cont...
Sort
View
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
14 years 1 months ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
MICRO
2007
IEEE
159views Hardware» more  MICRO 2007»
14 years 1 months ago
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation
As silicon process technology scales deeper into the nanometer regime, hardware defects are becoming more common. Such defects are bound to hinder the correct operation of future ...
Kypros Constantinides, Onur Mutlu, Todd M. Austin,...
HIPEAC
2005
Springer
14 years 1 months ago
Memory-Centric Security Architecture
Abstract. This paper presents a new security architecture for protecting software confidentiality and integrity. Different from the previous process-centric systems designed for ...
Weidong Shi, Chenghuai Lu, Hsien-Hsin S. Lee
SAMOS
2007
Springer
14 years 1 months ago
An Interrupt Controller for FPGA-based Multiprocessors
— Interrupt-based programming is widely used for interfacing a processor with peripherals and allowing software threads to interact. Many hardware/software architectures have bee...
Antonino Tumeo, Marco Branca, Lorenzo Camerini, Ma...
RSP
2007
IEEE
158views Control Systems» more  RSP 2007»
14 years 1 months ago
SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems
A widely used approach to avoid network intrusion is SNORT, an open source Network Intrusion Detection System (NIDS). This work describes SPP-NIDS, a architecture for intrusion de...
Luis Carlos Caruso, Guilherme Guindani, Hugo Schmi...