935 search results - page 11 / 187 » A New Statistical Optimization Algorithm for Gate Sizing |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Ignoring the effect of simultaneous switching for logic gates causes silicon failures for high performance microprocessor designs. The main reason to omit this effect is the run...
TVLSI
2008
13 years 7 months ago
2008
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors in...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires at...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
With shrinking technology, the timing variation of a digital circuit is becoming the most important factor while designing a functionally reliable circuit. Gate sizing has emerged...