Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness

The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations that are too expensive in computation for statistical circuit design. In this work, we develop an efficient SPICE simulation method and statistical transistor model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by sub-wavelength lithography and the gate etching process. By understanding the physical principles of atomistic simulations, we (a) identify the appropriate method to divide a non-uniform gate into slices in order to map those fluctuations into the device model; (b) extract the variation of Vth from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to Vth; and (c) propose a compact model of Vth variation that is scalable with gate size and...

• Type: Conference
• Year: 2008
• Where: DAC
• Authors: Yun Ye, Frank Liu, Sani R. Nassif, Yu Cao
• Keywords: DAC 2008, Design Automation, Gate Length Change, Gate Length Fluctuations, Vth Variation