935 search results - page 15 / 187 » A New Statistical Optimization Algorithm for Gate Sizing |
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
Reversible, or information-lossless, circuits have applications in digital signal processing, communication, computer graphics and cryptography. They are also a fundamental requir...
WEA
2010
Springer
14 years 2 months ago
2010
Springer
Abstract. A new technique for combinational logic optimization is described. The technique is a two-step process. In the first step, the nonlinearity of a circuit – as measured ...
ITC
1993
IEEE
13 years 11 months ago
1993
IEEE
This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented ...
ISPD
2003
ACM
14 years 28 days ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
BMCBI
2010
13 years 7 months ago
2010
Background: High throughput sequencing (HTS) platforms produce gigabases of short read (<100 bp) data per run. While these short reads are adequate for resequencing application...