62 search results - page 4 / 13 » A Non-binary Parallel Arithmetic Architecture |
IPPS
2010
IEEE
13 years 8 months ago
2010
IEEE
The advent of general purpose graphics processing units (GPGPU's) brings about a whole new platform for running numerically intensive applications at high speeds. Their multi-...
CODES
2003
IEEE
14 years 4 months ago
2003
IEEE
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
IPPS
2007
IEEE
14 years 5 months ago
2007
IEEE
This work addresses the problem of information leakage of cryptographic devices, by using the reconfiguration technique allied to an RNS based arithmetic. The information leaked b...
ASAP
2002
IEEE
14 years 3 months ago
2002
IEEE
This paper introduces PAPA: Packed Arithmetic on a Prefix Adder, a new approach to parallel prefix adder design that supports a wide variety of packed arithmetic computations, inc...
DAC
2007
ACM
14 years 12 months ago
2007
ACM
Three-Dimensional integration provides a simultaneous improvement in wire-related delay and power consumption of microprocessor circuits. Prior work has looked at the performance,...