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» A Note on Designing Logical Circuits Using SAT
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ISMVL
2006
IEEE
99views Hardware» more  ISMVL 2006»
14 years 1 months ago
Signal Processing Algorithms and Multiple-Valued Logic Design Methods
Multiple-valued logic can be viewed as an alternative approach to solving many problems in transmission, storage, and processing of large and even increasing amounts of informatio...
Jaakko Astola, Radomir S. Stankovic
EH
2003
IEEE
127views Hardware» more  EH 2003»
14 years 18 days ago
Comparing Different Serial and Parallel Heuristics to Design Combinational Logic Circuits
In this paper, we perform a comparative study of different heuristics used to design combinational logic circuits. The use of local search hybridized with a genetic algorithm and ...
Carlos A. Coello Coello, Enrique Alba, Gabriel Luq...
DAC
1994
ACM
13 years 11 months ago
Statistical Delay Modeling in Logic Design and Synthesis
Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay speci cations of manufactured circui...
Horng-Fei Jyu, Sharad Malik
DAC
2003
ACM
14 years 8 months ago
Behavioral consistency of C and verilog programs using bounded model checking
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
Edmund M. Clarke, Daniel Kroening, Karen Yorav
ISMVL
2008
IEEE
134views Hardware» more  ISMVL 2008»
14 years 1 months ago
Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells
Nanoscale multiple-valued logic systems require the development of nanometer scale integrated circuits and components. Due to limits in device physics, new components must be deve...
Theodore W. Manikas, Dale Teeters