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» A Note on Designing Logical Circuits Using SAT
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DATE
2005
IEEE
109views Hardware» more  DATE 2005»
14 years 28 days ago
Design Method for Constant Power Consumption of Differential Logic Circuits
Side channel attacks are a major security concern for smart cards and other embedded devices. They analyze the variations on the power consumption to find the secret key of the en...
Kris Tiri, Ingrid Verbauwhede
ARVLSI
2001
IEEE
305views VLSI» more  ARVLSI 2001»
13 years 11 months ago
Logic Design Considerations for 0.5-Volt CMOS
As the operating supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltag...
K. Joseph Hass, Jack Venbrux, Prakash Bhatia
DATE
2008
IEEE
126views Hardware» more  DATE 2008»
14 years 1 months ago
Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits
Metallic Carbon Nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Transistors (CNFETs), causing excessive leakage, degraded noise margin and delay variat...
Jie Zhang, Nishant Patil, Subhasish Mitra
JCIT
2008
144views more  JCIT 2008»
13 years 7 months ago
Design Methodology of a Controller to Forecast the Uncertain Cardiac Arrest Using Fuzzy Logic Approach
The main objective of design methodology of a controller for forecasting cardiac arrest using fuzzy logic approach is to provide the prediction of period of life time for the pati...
Nalayini Natarajan, Wahida Banu
DATE
2009
IEEE
103views Hardware» more  DATE 2009»
14 years 2 months ago
Masking timing errors on speed-paths in logic circuits
There is a growing concern about timing errors resulting from design marginalities and the effects of circuit aging on speed-paths in logic circuits. This paper presents a low ove...
Mihir R. Choudhury, Kartik Mohanram