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» A Note on Designing Logical Circuits Using SAT
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INFOCOM
2009
IEEE
14 years 2 months ago
Circuits/Cutsets Duality and a Unified Algorithmic Framework for Survivable Logical Topology Design in IP-over-WDM Optical Netwo
: Given a logical topology and a physical topology , the survivable logical topology design problem in an IP-overWDM optical network is to map the logical links into lightpaths in ...
Krishnaiyan Thulasiraman, Muhammad S. Javed, Guoli...
WCE
2007
13 years 8 months ago
Avoiding Hazards for Speed-Independent Logic Design
- In the speed-independent logic, the hazards caused by input inverters are identified. The known methods of the elimination of such hazards are based on avoiding input inverters. ...
Igor Lemberski
DAC
2004
ACM
14 years 8 months ago
A new heuristic algorithm for reversible logic synthesis
Reversible logic has applications in many fields, including quantum computing. Synthesis techniques for reversible circuits are not well developed, even for functions with a small...
Pawel Kerntopf
IOLTS
2008
IEEE
83views Hardware» more  IOLTS 2008»
14 years 1 months ago
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises s...
Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, ...
ACL2
2006
ACM
14 years 1 months ago
A SAT-based procedure for verifying finite state machines in ACL2
We describe a new procedure for verifying ACL2 properties about finite state machines (FSMs) using satisfiability (SAT) solving. We present an algorithm for converting ACL2 conj...
Warren A. Hunt Jr., Erik Reeber