522 search results - page 21 / 105 » A Note on Designing Logical Circuits Using SAT |
DATE
2010
IEEE
14 years 13 days ago
2010
IEEE
Ambipolar devices have been reported in many technologies, including carbon nanotube field effect transistors (CNTFETs). The ambipolarity can be in-field controlled with a secon...
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an ex...
CJ
2010
13 years 7 months ago
2010
rder logic (HOL) theorem prover. The high ability of abstraction in the HOL verification system allows its use for the verification task over the whole design path of the circuit, ...