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» A Note on Designing Logical Circuits Using SAT
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MSE
1999
IEEE
204views Hardware» more  MSE 1999»
13 years 11 months ago
A PC-based Educational Tool for CMOS Integrated Circuit Design
This paper presents a PC based software running on PC dedicated to the training in sub-micron CMOS VLSI design. The software firstly consists in a HDL-based schematic editor with ...
Etienne Sicard, Chen Xi
ASYNC
2002
IEEE
114views Hardware» more  ASYNC 2002»
14 years 10 days ago
Checking Delay-Insensitivity: 104 Gates and Beyond
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits ...
Alex Kondratyev, Oriol Roig, Lawrence Neukom, Karl...
VLSID
2005
IEEE
139views VLSI» more  VLSID 2005»
14 years 7 months ago
Variable Input Delay CMOS Logic for Low Power Design
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
DAC
2002
ACM
14 years 8 months ago
IP delivery for FPGAs using Applets and JHDL
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
Michael J. Wirthlin, Brian McMurtrey
PATMOS
2004
Springer
14 years 21 days ago
Leakage Power Analysis and Comparison of Deep Submicron Logic Gates
Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to tran...
Geoff V. Merrett, Bashir M. Al-Hashimi