522 search results - page 37 / 105 » A Note on Designing Logical Circuits Using SAT |
120
Voted
GLVLSI
1999
IEEE
15 years 7 months ago
1999
IEEE
Despite the seemingly endless upwards spiral of modern VLSI technology, many experts are predicting a hard wall for CMOS in about a decade. Given this, researchers continue to loo...
110
Voted
ICCAD
1999
IEEE
15 years 7 months ago
1999
IEEE
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaust...
113
Voted
FPGA
2007
ACM
15 years 9 months ago
2007
ACM
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...
122
Voted
ASPDAC
2008
ACM
15 years 4 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
79
Voted
ASPDAC
2007
ACM
15 years 6 months ago
2007
ACM
Abstract-- A complementary ferroelectriccapacitor (CFC) logic-circuit style is proposed for a compact and standby-power-free content-addressable memory (CAM). Since the use of the ...