522 search results - page 42 / 105 » A Note on Designing Logical Circuits Using SAT |
TCAD
2008
13 years 7 months ago
2008
Abstract--Designers and high-level synthesis tools can introduce unwanted cycles in digital circuits, and for certain combinational functions, cyclic circuits that are stable and d...
ISQED
2003
IEEE
14 years 20 days ago
2003
IEEE
- This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a cha...
ICCAD
1996
IEEE
13 years 11 months ago
1996
IEEE
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...
DSD
2010
IEEE
13 years 4 months ago
2010
IEEE
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementati...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Design and verification of systems at the Register-Transfer (RT) or behavioral level require the ability to reason at higher levels of abstraction. Difference logic consists of an...