522 search results - page 68 / 105 » A Note on Designing Logical Circuits Using SAT |
CHES
2005
Springer
14 years 1 months ago
2005
Springer
During the last years, several logic styles that counteract side-channel attacks have been proposed. They all have in common that their level of resistance heavily depends on imple...
ICCAD
1998
IEEE
14 years 9 days ago
1998
IEEE
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
PATMOS
2005
Springer
14 years 1 months ago
2005
Springer
This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to max...
ICCD
2007
IEEE
14 years 5 months ago
2007
IEEE
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globa...
TVLSI
2002
13 years 7 months ago
2002
Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra lar...