522 search results - page 70 / 105 » A Note on Designing Logical Circuits Using SAT |
142
Voted
ICCAD
1996
IEEE
15 years 7 months ago
1996
IEEE
The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper...
133
Voted
JELIA
2004
Springer
15 years 8 months ago
2004
Springer
We briefly overview the most recent improvements we have incorporated to the existent implementations of the TAS methodology, the simplified ∆-tree representation of formulas i...
84
Voted
ATS
1998
IEEE
15 years 7 months ago
1998
IEEE
This paper presents the design and simulation method for developing a RISC-based 32-bit embedded on-board computer. Instead of the conventional breadboarded prototype, (1) we used...
112
Voted
ASYNC
2003
IEEE
15 years 8 months ago
2003
IEEE
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...
119
Voted
DAC
2002
ACM
16 years 3 months ago
2002
ACM
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...