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» A Note on Designing Logical Circuits Using SAT
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TCAD
2008
172views more  TCAD 2008»
13 years 8 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
14 years 8 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...
ISQED
2002
IEEE
106views Hardware» more  ISQED 2002»
14 years 27 days ago
Trading off Reliability and Power-Consumption in Ultra-low Power Systems
Critical systems like pace-makers, defibrillators, wearable computers and other electronic gadgets have to be designed not only for reliability but also for ultra-low power consu...
Atul Maheshwari, Wayne Burleson, Russell Tessier
DAC
2007
ACM
14 years 9 months ago
Global Critical Path: A Tool for System-Level Timing Analysis
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...
SIGIR
2003
ACM
14 years 1 months ago
HAT: a hardware assisted TOP-DOC inverted index component
A novel Hardware Assisted Top-Doc (HAT) component is disclosed. HAT is an optimized content indexing device based on a modified inverted index structure. HAT accommodates patterns...
S. Kagan Agun, Ophir Frieder