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» A Note on Designing Logical Circuits Using SAT
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ISCA
2009
IEEE
159views Hardware» more  ISCA 2009»
14 years 2 months ago
End-to-end register data-flow continuous self-test
While Moore’s Law predicts the ability of semi-conductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in t...
Javier Carretero, Pedro Chaparro, Xavier Vera, Jau...
SIGMOD
2012
ACM
212views Database» more  SIGMOD 2012»
11 years 10 months ago
Local structure and determinism in probabilistic databases
While extensive work has been done on evaluating queries over tuple-independent probabilistic databases, query evaluation over correlated data has received much less attention eve...
Theodoros Rekatsinas, Amol Deshpande, Lise Getoor
FPGA
2004
ACM
234views FPGA» more  FPGA 2004»
13 years 11 months ago
An embedded true random number generator for FPGAs
Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. Until recently, designers using FPGAs had le...
Paul Kohlbrenner, Kris Gaj
TASE
2008
IEEE
13 years 8 months ago
Modeling and Supervisory Control of Railway Networks Using Petri Nets
In this paper we deal with the problem of modeling railway networks with Petri nets so as to apply the theory of supervisory control for discrete event systems to automatically de...
Alessandro Giua, Carla Seatzu
DAC
2001
ACM
14 years 9 months ago
A True Single-Phase 8-bit Adiabatic Multiplier
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthy...