522 search results - page 94 / 105 » A Note on Designing Logical Circuits Using SAT |
DAC
2009
ACM
14 years 9 months ago
2009
ACM
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
PADS
2003
ACM
14 years 1 months ago
2003
ACM
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...
ICIP
2004
IEEE
14 years 9 months ago
2004
IEEE
H.264/AVC is a new international standard for the compression of natural video images, in which a deblocking filter has been adopted to remove blocking artifacts. In this paper, w...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
As timing requirements in today’s advanced VLSI designs become more aggressive, the need for automated tools to diagnose timing failures increases. This work presents two such a...