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» A Novel Approach for Hardware Based Sound Classification
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DATE
2009
IEEE
134views Hardware» more  DATE 2009»
15 years 10 months ago
Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures
We address the problem of real-time streaming applications scheduling on hybrid CPU/FPGA architectures. The main contribution is a two-step approach to minimize the buffer require...
Jun Zhu, Ingo Sander, Axel Jantsch
AHS
2007
IEEE
253views Hardware» more  AHS 2007»
15 years 10 months ago
evolFIR: Evolving redundancy-free FIR structures
Finite impulse response (FIR) structures are the most commonly used digital filters and can be found in various areas of everyday life. In this paper we introduce a novel approac...
Szilvia Zvada, Gabriella Kókai, Róbe...
ETS
2007
IEEE
109views Hardware» more  ETS 2007»
15 years 10 months ago
Test Configurations for Diagnosing Faulty Links in NoC Switches
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address dri...
Jaan Raik, Raimund Ubar, Vineeth Govind
109
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ISQED
2007
IEEE
109views Hardware» more  ISQED 2007»
15 years 10 months ago
Virtual Channels Planning for Networks-on-Chip
The virtual channel flow control (VCFC) provides an efficient implementation for on-chip networks. However, allocating the virtual channels (VCs) uniformly results in a waste of a...
Ting-Chun Huang, Ümit Y. Ogras, Radu Marcules...
DATE
2006
IEEE
176views Hardware» more  DATE 2006»
15 years 10 months ago
Low power synthesis of dynamic logic circuits using fine-grained clock gating
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Mei...