22 search results - page 4 / 5 » A Novel Asynchronous Software Cache Implementation for the C... |
ASPLOS
2010
ACM
14 years 2 months ago
2010
ACM
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...
CODES
2009
IEEE
13 years 11 months ago
2009
IEEE
Profilers play an important role in software/hardware design, optimization, and verification. Various approaches have been proposed to implement profilers. The most widespread app...
ISPDC
2010
IEEE
13 years 6 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
OOPSLA
2009
Springer
14 years 2 months ago
2009
Springer
Software has spent the bounty of Moore’s law by solving harder problems and exploiting abstractions, such as highlevel languages, virtual machine technology, binary rewritdynami...
MICRO
2003
IEEE
14 years 25 days ago
2003
IEEE
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...