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» A Novel Method to Improve the Test Efficiency of VLSI Tests
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ASPDAC
2004
ACM
151views Hardware» more  ASPDAC 2004»
14 years 27 days ago
Combinatorial group testing methods for the BIST diagnosis problem
— We examine an abstract formulation of BIST diagnosis in digital logic systems. The BIST diagnosis problem has applications that include identification of erroneous test vector...
Andrew B. Kahng, Sherief Reda
VLSISP
2010
148views more  VLSISP 2010»
13 years 5 months ago
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive
Abstract Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementatio...
Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunso...
DATE
2008
IEEE
112views Hardware» more  DATE 2008»
14 years 1 months ago
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in o...
Paolo Bernardi, Matteo Sonza Reorda
VLSID
2001
IEEE
82views VLSI» more  VLSID 2001»
14 years 7 months ago
Efficient Signature-Based Fault Diagnosis Using Variable Size Windows
A technique for signature based diagnosis using windows of different sizes is presented. It allows to obtain increased diagnostic information from a given test at a lower cost, wi...
Thomas Clouqueur, Ozen Ercevik, Kewal K. Saluja, H...
VLSID
1993
IEEE
136views VLSI» more  VLSID 1993»
13 years 11 months ago
A Simulation-Based Test Generation Scheme Using Genetic Algorithms
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
M. Srinivas, Lalit M. Patnaik