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» A Novel Method to Improve the Test Efficiency of VLSI Tests
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PVLDB
2008
108views more  PVLDB 2008»
13 years 7 months ago
Taming verification hardness: an efficient algorithm for testing subgraph isomorphism
Graphs are widely used to model complicated data semantics in many applications. In this paper, we aim to develop efficient techniques to retrieve graphs, containing a given query...
Haichuan Shang, Ying Zhang, Xuemin Lin, Jeffrey Xu...
GECCO
2006
Springer
162views Optimization» more  GECCO 2006»
13 years 11 months ago
Improving evolutionary real-time testing
Embedded systems are often used in a safety-critical context, e.g. in airborne or vehicle systems. Typically, timing constraints must be satisfied so that real-time embedded syste...
Marouane Tlili, Stefan Wappler, Harmen Sthamer
DATE
2010
IEEE
149views Hardware» more  DATE 2010»
13 years 11 months ago
Efficient decision ordering techniques for SAT-based test generation
Model checking techniques are promising for automated generation of directed tests. However, due to the prohibitively large time and resource requirements, conventional model chec...
Mingsong Chen, Xiaoke Qin, Prabhat Mishra
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
14 years 4 months ago
A Novel Low-Power Scan Design Technique Using Supply Gating
— Reduction in test power is important to improve battery life in portable devices employing periodic self-test, to increase reliability of testing and to reduce test-cost. In sc...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukh...
DAC
2004
ACM
14 years 8 months ago
Efficient on-line testing of FPGAs with provable diagnosabilities
We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than ...
Vinay Verma, Shantanu Dutt, Vishal Suthar