130 search results - page 5 / 26 » A Novel Metric for Interconnect Architecture Performance |
DAC
2004
ACM
14 years 8 months ago
2004
ACM
For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined g...
FPGA
2004
ACM
14 years 1 months ago
2004
ACM
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
High-radix switches are desirable building blocks for large computer interconnection networks, because they are more suitable to convert chip I/O bandwidth into low latency and lo...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...
ISCA
2007
IEEE
14 years 2 months ago
2007
IEEE
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...