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ARC
2009
Springer
134views Hardware» more  ARC 2009»
14 years 8 days ago
A HyperTransport 3 Physical Layer Interface for FPGAs
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
Heiner Litz, Holger Fröning, Ulrich Brün...
FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
14 years 3 days ago
A crosstalk-aware timing-driven router for FPGAs
As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstal...
Steven J. E. Wilton
ARC
2009
Springer
140views Hardware» more  ARC 2009»
14 years 2 months ago
FPGA-Based Anomalous Trajectory Detection Using SOFM
A system for automatically classifying the trajectory of a moving object in a scene as usual or suspicious is presented. The system uses an unsupervised neural network (Self Organi...
Kofi Appiah, Andrew Hunter, Tino Kluge, Philip Aik...
ISCAS
1995
IEEE
91views Hardware» more  ISCAS 1995»
13 years 11 months ago
An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays
Abstract -- Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmab...
W. Eatherton, J. Kelly, T. Schiefelbein, H. Pottin...
FPGA
2007
ACM
153views FPGA» more  FPGA 2007»
14 years 1 months ago
GlitchLess: an active glitch minimization technique for FPGAs
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...