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» A Parallel Hardware Architecture for Image Feature Detection
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LCPC
1999
Springer
14 years 28 days ago
Compiling for Speculative Architectures
The traditional target machine of a parallelizing compiler can execute code sections either serially or in parallel. In contrast, targeting the generated code to a speculative para...
Seon Wook Kim, Rudolf Eigenmann
SC
2004
ACM
14 years 2 months ago
A Parallel Implementation of 4-Dimensional Haralick Texture Analysis for Disk-Resident Image Datasets
Texture analysis is one possible method to detect features in biomedical images. During texture analysis, texture related information is found by examining local variations in ima...
Brent Woods, Bradley D. Clymer, Joel H. Saltz, Tah...
CODES
2005
IEEE
14 years 2 months ago
An architectural level design methodology for embedded face detection
Face detection and recognition research has attracted great attention in recent years. Automatic face detection has great potential in a large array of application areas, includin...
Vida Kianzad, Sankalita Saha, Jason Schlessman, Ga...
IEEEPACT
2006
IEEE
14 years 2 months ago
Self-checking instructions: reducing instruction redundancy for concurrent error detection
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
HPCA
2007
IEEE
14 years 9 months ago
LogTM-SE: Decoupling Hardware Transactional Memory from Caches
This paper proposes a hardware transactional memory (HTM) system called LogTM Signature Edition (LogTM-SE). LogTM-SE uses signatures to summarize a transaction's readand writ...
Luke Yen, Jayaram Bobba, Michael R. Marty, Kevin E...