Self-checking instructions: reducing instruction redundancy for concurrent error detection

With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi-threading (RMT) is an attractive approach for concurrent error detection. However, redundant thread execution has a significant impact on performance and energy consumption in the chip. In this paper, we propose reducing instruction redundancy (the instructions that are redundantly executed) as a means to mitigate the performance and energy impact of redundancy. In this paper, we experiment with an decoupled RMT approach where the frontend pipeline stages are protected through error codes, while the backend pipeline stages are protected through redundant execution. In this approach, we define two categories of instructions — self-checking and semi self-checking instructions. Self checking instructions are those instructions whose results are checked for any errors when their “main” copies are execute...

• Type: Conference
• Year: 2006
• Where: IEEEPACT
• Authors: Sumeet Kumar, Aneesh Aggarwal
• Keywords: Hardware, IEEEPACT 2006, Instruction, Instruction Redundancy, Semi Self-checking Instructions