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» A Parallel Hardware Architecture for Image Feature Detection
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MICRO
2009
IEEE
132views Hardware» more  MICRO 2009»
14 years 3 months ago
EazyHTM: eager-lazy hardware transactional memory
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulka...
EDOC
2007
IEEE
14 years 3 months ago
Modeling and Integrating Aspects into Component Architectures
Dependable software systems are difficult to develop because developers must understand and address several interdependent and pervasive dependability concerns. Features that addr...
Lydia Michotte, Robert B. France, Franck Fleurey
ISCAS
2002
IEEE
190views Hardware» more  ISCAS 2002»
14 years 1 months ago
A high performance JPEG2000 architecture
—JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for diverse data dissemination. These features are possible due to adaptation of ...
Kishore Andra, Chaitali Chakrabarti, Tinku Acharya
SPIESR
1996
118views Database» more  SPIESR 1996»
13 years 10 months ago
Performances of Multiprocessor Multidisk Architectures for Continuous Media Storage
Multimedia interfaces increase the need for large image databases, capable of storing and reading streams of data with strict synchronicity and isochronicity requirements. In orde...
Benoit A. Gennart, Vincent Messerli, Roger D. Hers...
JEI
2000
133views more  JEI 2000»
13 years 8 months ago
Low complexity block motion estimation using morphological-based feature extraction and XOR operations
Motion estimation is a temporal image compression technique, where an n x n block of pixels in the current frame of a video sequence is represented by a motion vector with respect...
Thinh M. Le, R. Mason, Sethuraman Panchanathan