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» A Parallel Hardware Architecture for Image Feature Detection
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HPCA
2007
IEEE
14 years 3 months ago
Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures
To provide high dependability in a multithreaded system despite hardware faults, the system must detect and correct errors in its shared memory system. Recent research has explore...
Albert Meixner, Daniel J. Sorin
VISUALIZATION
1996
IEEE
14 years 26 days ago
Real-Time Incremental Visualization of Dynamic Ultrasound Volumes Using Parallel BSP Trees
We present a method for producing real-time volume visualizations of continuously captured, arbitrarily-oriented 2D arrays (slices) of data. Our system constructs a 3D representat...
William F. Garrett, Henry Fuchs, Mary C. Whitton, ...
IEEEPACT
2000
IEEE
14 years 1 months ago
Global Register Partitioning
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
Jason Hiser, Steve Carr, Philip H. Sweany
ISCA
2009
IEEE
199views Hardware» more  ISCA 2009»
14 years 3 months ago
SigRace: signature-based data race detection
Detecting data races in parallel programs is important for both software development and production-run diagnosis. Recently, there have been several proposals for hardware-assiste...
Abdullah Muzahid, Darío Suárez Graci...
AAAI
1990
13 years 10 months ago
The Design of a Marker Passing Architecture for Knowledge Processing
Knowledge processing is very demanding on computer architectures. Knowledge processing generates subcomputation paths at an exponential rate. It is memory intensive and has high c...
Wing Lee, Dan I. Moldovan