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» A Parallel Hardware Architecture for Image Feature Detection
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ISCA
2011
IEEE
287views Hardware» more  ISCA 2011»
13 years 12 days ago
Scalable power control for many-core architectures running multi-threaded applications
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
Kai Ma, Xue Li, Ming Chen, Xiaorui Wang
WACV
2005
IEEE
14 years 2 months ago
Combining View-Based and Model-Based Tracking of Articulated Human Movements
Many existing systems for human body tracking are based on dynamic model-based tracking that is driven by local image features. Alternatively, within a view-based approach, tracki...
Cristóbal Curio, Martin A. Giese
ICCS
2009
Springer
13 years 6 months ago
Evaluating the Jaccard-Tanimoto Index on Multi-core Architectures
The Jaccard/Tanimoto coefficient is an important workload, used in a large variety of problems including drug design fingerprinting, clustering analysis, similarity web searching a...
Vipin Sachdeva, Douglas M. Freimuth, Chris Mueller
CCGRID
2004
IEEE
14 years 13 days ago
DWDM-RAM: a data intensive Grid service architecture enabled by dynamic optical networks
Next generation applications and architectures (for example, Grids) are driving radical changes in the nature of traffic, service models, technology, and cost, creating opportunit...
Tal Lavian, Joe Mambretti, Doug Cutrell, Howard J....
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
14 years 9 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das