471 search results - page 80 / 95 » A Parallel Hardware Architecture for Image Feature Detection |
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
HPCA
2008
IEEE
14 years 3 months ago
2008
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
ICDCS
2010
IEEE
13 years 8 months ago
2010
IEEE
In this paper, we present 3DLoc: an integrated system of hardware and software toolkits for locating an 802.11compliant mobile device in a three dimensional (3D) space. 3DLoc feat...
ANCS
2007
ACM
14 years 19 days ago
2007
ACM
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
HICSS
2003
IEEE
14 years 1 months ago
2003
IEEE
Video information, image processing and computer vision techniques are developing rapidly nowadays because of the availability of acquisition, processing and editing tools, which ...