31 search results - page 1 / 7 » A Parallel and Modular Architecture for 802.16e LDPC Codes |
DSD
2008
IEEE
14 years 2 months ago
2008
IEEE
We propose a parallel and modular architecture well suited to 802.16e WiMax LDPC code decoding. The proposed design is fully compliant with all the code classes defined by the Wi...
FCCM
2008
IEEE
14 years 2 months ago
2008
IEEE
We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the...
VTC
2008
IEEE
14 years 2 months ago
2008
IEEE
—In this paper, we propose a class of implementation friendly structured LDPC codes with low error floors. The proposed codes exhibit no apparent error floors as compared with qu...
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
Abstract— We present the concepts and realization of a highly parallelized decoder architecture for LDPC convolutional codes and tailbiting LDPC convolutional codes. This archite...
SIPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...