204 search results - page 24 / 41 » A Pipelined Memory Architecture for High Throughput Network ... |
EUROPDS
1997
13 years 9 months ago
1997
In this paper, we follow a new path to arrive at the idea of a COMA — a Cache Only Memory Architecture. We show how the evolution of another architecture (ADARC) leads quite nat...
EUROPAR
1997
Springer
13 years 11 months ago
1997
Springer
The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Access to remote memory is likely to ...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of...
ICNS
2007
IEEE
14 years 1 months ago
2007
IEEE
To build holistic protection against complex and blended network threats, multiple security features need to be integrated into a unified security architecture, which requires in ...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...