204 search results - page 39 / 41 » A Pipelined Memory Architecture for High Throughput Network ... |
VLSISP
1998
13 years 7 months ago
1998
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
TC
2011
13 years 2 months ago
2011
—CMOS scaling has long been a source of dramatic performance gains. However, semiconductor feature size reduction has resulted in increasing levels of operating temperatures and ...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leadin...
COMPUTING
2004
13 years 7 months ago
2004
The presented image registration method uses a regularized gradient flow to correlate the intensities in two images. Thereby, an energy functional is successively minimized by des...