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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 7 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
13 years 11 months ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
ANCS
2006
ACM
13 years 11 months ago
Efficient memory utilization on network processors for deep packet inspection
Deep Packet Inspection (DPI) refers to examining both packet header and payload to look for predefined patterns, which is essential for network security, intrusion detection and c...
Piti Piyachon, Yan Luo
ISCA
1997
IEEE
108views Hardware» more  ISCA 1997»
13 years 11 months ago
The SGI Origin: A ccNUMA Highly Scalable Server
The SGI Origin 2000 is a cache-coherent non-uniform memory access (ccNUMA) multiprocessor designed and manufactured by Silicon Graphics, Inc. The Origin system was designed from t...
James Laudon, Daniel Lenoski
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
14 years 24 days ago
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors
This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the domi...
Alberto Macii, Enrico Macii, Fabrizio Crudo, Rober...