204 search results - page 7 / 41 » A Pipelined Memory Architecture for High Throughput Network ... |
ISSS
1997
IEEE
13 years 11 months ago
1997
IEEE
Given a hardware/software partitioned specification and an allocation (number and type) of processors, we present an algorithm to (1) map each of the software behaviors (or tasks...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
NOCS
2010
IEEE
13 years 5 months ago
2010
IEEE
Router microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forw...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
INFOCOM
2010
IEEE
13 years 6 months ago
2010
IEEE
—Dictionary-Based String Matching (DBSM) is used in network Deep Packet Inspection (DPI) applications virus scanning [1] and network intrusion detection [2]. We propose the Pipel...