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» A Probabilistic Approach to Buffer Insertion
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ICCAD
2005
IEEE
168views Hardware» more  ICCAD 2005»
14 years 3 months ago
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
— Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock t...
Jeng-Liang Tsai, Lizheng Zhang
ICCAD
2002
IEEE
100views Hardware» more  ICCAD 2002»
13 years 12 months ago
Optimal buffered routing path constructions for single and multiple clock domain systems
Shrinking process geometries and the increasing use of IP components in SoC designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-c...
Soha Hassoun, Charles J. Alpert, Meera Thiagarajan
WCRE
2005
IEEE
14 years 18 days ago
Enhancing Security Using Legality Assertions
Buffer overflows have been the most common form of security vulnerability in the past decade. A number of techniques have been proposed to address such attacks. Some are limited t...
Lei Wang, James R. Cordy, Thomas R. Dean
SPAA
2009
ACM
14 years 7 months ago
Dynamic external hashing: the limit of buffering
Hash tables are one of the most fundamental data structures in computer science, in both theory and practice. They are especially useful in external memory, where their query perf...
Zhewei Wei, Ke Yi, Qin Zhang
ICCAD
2004
IEEE
110views Hardware» more  ICCAD 2004»
14 years 3 months ago
Wire-length prediction using statistical techniques
We address the classic wire-length estimation problem and propose a new statistical wire-length estimation approach that captures the probability distribution function of net leng...
Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwa...