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DATE
2000
IEEE
142views Hardware» more  DATE 2000»
14 years 4 days ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
ITC
2003
IEEE
158views Hardware» more  ITC 2003»
14 years 1 months ago
Extraction Error Diagnosis and Correction in High-Performance Designs
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikara...
POPL
2002
ACM
14 years 8 months ago
Functional logic overloading
Functional logic overloading is a novel approach to userdefined overloading that extends Haskell's concept of type classes in significant ways. Whereas type classes are conce...
Matthias Neubauer, Peter Thiemann, Martin Gasbichl...
ASAP
1997
IEEE
156views Hardware» more  ASAP 1997»
13 years 12 months ago
Design methodology for digital signal processing
Improvements in semiconductor integration density and the resulting problem of having to manage designs of increasing complexity is an old one, but still current. The new challeng...
Gerhard Fettweis
ASAP
2004
IEEE
115views Hardware» more  ASAP 2004»
13 years 11 months ago
A Low-Power Carry Skip Adder with Fast Saturation
In this paper, we present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipat...
Michael J. Schulte, Kai Chirca, John Glossner, Hao...