Scan chain insertion can have large impact on routability, wirelength and timing. We propose a routing-driven and timing-aware methodology for scan insertion with minimum wireleng...
Abstract— For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation...
Scan chains are widely used to improve the testability of IC designs. In traditional 2D IC designs, various design techniques on the construction of scan chains have been proposed...
It has been proven that scan path is a potent hazard for secure chips. Scan based attacks have been recently demonstrated against DES or AES and several solutions have been presen...
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...