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VTC
2008
IEEE
124views Communications» more  VTC 2008»
14 years 1 months ago
Long Length LDPC Code Construction and the Corresponding Decoder Implementation with Adjustable Parallelism
—In this paper, we propose a class of implementation friendly structured LDPC codes with low error floors. The proposed codes exhibit no apparent error floors as compared with qu...
Chia-Yu Lin, Mong-Kai Ku, Yi-Hsing Chien
ISLPED
2010
ACM
206views Hardware» more  ISLPED 2010»
13 years 7 months ago
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija
CATA
2010
13 years 7 months ago
A Hardware Implementation of the Advanced Encryption Standard (AES) Algorithm using SystemVerilog
In this paper, a hardware implementation of the AES128 encryption algorithm is proposed. A unique feature of the proposed pipelined design is that the round keys, which are consum...
Bahram Hakhamaneshi, Behnam S. Arad
IPPS
2006
IEEE
14 years 1 months ago
Implementation of a programmable array processor architecture for approximate string matching algorithms on FPGAs
Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array p...
Panagiotis D. Michailidis, Konstantinos G. Margari...
PDP
2002
IEEE
14 years 9 days ago
A Parametrized Algorithm that Implements Sequential, Causal, and Cache Memory Consistency
In this paper we present an algorithm that can be used to implement sequential, causal, or cache consistency in distributed shared memory (DSM) systems. For this purpose it has a ...
Ernesto Jiménez, Antonio Fernández, ...