Double precision floating-point arithmetic is inadequate for many scientific computations. This paper presents the design of a quadruple precision floating-point multiplier tha...
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia
—With systems such as Road Runner, there is a trend in super computing to offload parallel tasks to special purpose co-processors, composed of many relatively simple scalar proc...
Matthew Badin, Lubomir Bic, Michael B. Dillencourt...
We introduce a novel left-to-right leading digit first dual recoding of an operand for the purpose of designing the squaring operation on that operand. Our dual recoding yields an...