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DAC
1994
ACM
13 years 12 months ago
The Design of High-Performance Microprocessors at Digital
Today's high-performance single-chip CMOS microprocessors are the most complex and challenging chip designs ever implemented. To stay on the leading edge, Digital's micro...
Thomas F. Fox
EUROPAR
2000
Springer
13 years 11 months ago
Novel Models for Or-Parallel Logic Programs: A Performance Analysis
One of the advantages of logic programming is the fact that it offers many sources of implicit parallelism, such as and-parallelism and or-parallelism. Arguably, or-parallel system...
Vítor Santos Costa, Ricardo Rocha, Fernando...
VLSID
2009
IEEE
143views VLSI» more  VLSID 2009»
14 years 8 months ago
SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems
Dynamic reconfiguration techniques are widely used for efficient system optimization. Dynamic cache reconfiguration is a promising approach for reducing energy consumption as well...
Weixun Wang, Prabhat Mishra, Ann Gordon-Ross
VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
14 years 8 months ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne
ISCC
2005
IEEE
14 years 1 months ago
Describing Multidimensional Schedules for Media-Access Control in Time-Triggered Communication
A shared communication medium is characterized by multiple entities that use this medium by reading and writing from and to it. Write operations on the shared communication medium...
Sebastian Fischmeister